/*
 * Copyright(c) 2015-2019 Xilinx, Inc. All rights reserved.
 *
 * BSD LICENSE
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   * Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   * Neither the name of the copyright holder nor the names of its
 *     contributors may be used to endorse or promote products derived
 *     from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef XCMAC_HW_H /* prevent circular inclusions */
#define XCMAC_HW_H /* by using protection macros */

/** @name Registers
 *
 * Register offsets for xcmac device.
 * @{
 */

/* Configuration Registers */
#define XCMAC_GT_RESET_REG_OFFSET 0x0000
#define XCMAC_RESET_REG_OFFSET 0x0004
#define XCMAC_MODE_REG_OFFSET 0x0008
#define XCMAC_CONFIGURATION_TX_REG1_OFFSET 0x00C
/* Reserved 0x10 */
#define XCMAC_CONFIGURATION_RX_REG1_OFFSET 0x0014

#define XCMAC_CORE_MODE_REG_OFFSET 0x0020

#define XCMAC_CMAC_VERSION_REG_OFFSET 0x0024
/* Reserved 0x28 */
#define XCMAC_CONFIG_TX_BIP_OVERRIDE_OFFSET 0x002C
/* Tx flow control regs */
#define XCMAC_CONFIG_TX_FLOW_CONTROL_REG1_OFFSET 0x0030
#define XCMAC_CONFIG_TX_FLOW_CONTROL_REFRESH_REG1_OFFSET 0x0034
#define XCMAC_CONFIG_TX_FLOW_CONTROL_REFRESH_REG2_OFFSET 0x0038
#define XCMAC_CONFIG_TX_FLOW_CONTROL_REFRESH_REG3_OFFSET 0x003C
#define XCMAC_CONFIG_TX_FLOW_CONTROL_REFRESH_REG4_OFFSET 0x0040
#define XCMAC_CONFIG_TX_FLOW_CONTROL_REFRESH_REG5_OFFSET 0x0044
#define XCMAC_CONFIG_TX_FLOW_CONTROL_QUANTA_REG1_OFFSET 0x0048
#define XCMAC_CONFIG_TX_FLOW_CONTROL_QUANTA_REG2_OFFSET 0x004C
#define XCMAC_CONFIG_TX_FLOW_CONTROL_QUANTA_REG3_OFFSET 0x0050
#define XCMAC_CONFIG_TX_FLOW_CONTROL_QUANTA_REG4_OFFSET 0x0054
#define XCMAC_CONFIG_TX_FLOW_CONTROL_QUANTA_REG5_OFFSET 0x0058

#define XCMAC_CONFIG_TX_OTN_PKT_LEN_REG_OFFSET 0x005C
#define XCMAC_CONFIG_TX_OTN_CTL_REG_OFFSET 0x0060

/* Rx flow control regs */
#define CONFIGURATION_RX_FLOW_CONTROL_REG1_OFFSET 0x0084
#define CONFIGURATION_RX_FLOW_CONTROL_REG2_OFFSET 0x0088

#define XCMAC_GT_LOOPBACK_REG_OFFSET 0x0090

/* Auto Negotiation and Link Training Configuration registers */
#define XCMAC_CONFIG_AN_CONTROL_REG1_OFFSET 0x00A0
#define XCMAC_CONFIG_AN_CONTROL_REG2_OFFSET 0x00A4
#define XCMAC_CONFIG_AN_ABILITY_OFFSET 0x00A8

#define XCMAC_CONFIG_LT_CONTROL_REG1_OFFSET 0x00AC
#define XCMAC_CONFIG_LT_TRAINED_REG_OFFSET 0x00B0
#define XCMAC_CONFIG_LT_PRESET_REG_OFFSET 0x00B4
#define XCMAC_CONFIG_LT_INIT_REG_OFFSET 0x00B8
#define XCMAC_CONFIG_LT_SEED_REG0_OFFSET 0x00BC
#define XCMAC_CONFIG_LT_SEED_REG1_OFFSET 0x00C0
#define XCMAC_CONFIG_LT_COEFFICIENT_REG0_OFFSET 0x00C4
#define XCMAC_CONFIG_LT_COEFFICIENT_REG1_OFFSET 0x00C8

/* status and Statistics Register Map */
#define XCMAC_STAT_TX_STATUS_OFFSET 0x200
#define XCMAC_STAT_RX_STATUS_OFFSET 0x204
#define XCMAC_STAT_STATUS_OFFSET 0x208
#define XCMAC_STAT_RX_BLOCK_LOCK_OFFSET 0x20c
#define XCMAC_STAT_RX_SYNCED_OFFSET 0x210
#define XCMAC_STAT_RX_SYNCED_ERR_OFFSET 0x214
#define XCMAC_STAT_RX_MF_ERR_OFFSET 0x218
#define XCMAC_STAT_RX_MF_LEN_ERR_OFFSET 0x21c
#define XCMAC_STAT_RX_MF_REPEAT_ERR_OFFSET 0x220
#define XCMAC_STAT_RX_VL_DEMUXED_OFFSET 0x224
#define XCMAC_STAT_RX_VL_NUM_0_OFFSET 0x228
#define XCMAC_STAT_RX_VL_NUM_6_OFFSET 0x22c
#define XCMAC_STAT_RX_VL_NUM_12_OFFSET 0x230
#define XCMAC_STAT_RX_VL_NUM_18_OFFSET 0x234
#define STAT_RX_BIP_OVERRIDE_OFFSET 0x238
#define XCMAC_STAT_TX_OTN_STATUS_OFFSET 0x023C

/* Auto negotiation and link training */
#define XCMAC_STAT_AN_STATUS_OFFSET 0x0258
#define XCMAC_STAT_AN_ABILITY_OFFSET 0x025C
#define XCMAC_STAT_AN_LINK_CTL_OFFSET 0x0260
#define XCMAC_STAT_LT_STATUS_REG1_OFFSET 0x0264
#define XCMAC_STAT_LT_STATUS_REG2_OFFSET 0x0268
#define XCMAC_STAT_LT_STATUS_REG3_OFFSET 0x026C
#define XCMAC_STAT_LT_STATUS_REG4_OFFSET 0x0270

#define XCMAC_TICK_REG_OFFSET 0x2b0
#define XCMAC_STAT_CYCLE_COUNT_OFFSET 0x2b8
/* BIP8 Error Counts regs */
#define XCMAC_STAT_RX_BIP_ERR_0_OFFSET 0x2c0
#define XCMAC_STAT_RX_BIP_ERR_1_OFFSET 0x2c8
#define XCMAC_STAT_RX_BIP_ERR_2_OFFSET 0x2d0
#define XCMAC_STAT_RX_BIP_ERR_3_OFFSET 0x2d8
#define XCMAC_STAT_RX_BIP_ERR_4_OFFSET 0x2e0
#define XCMAC_STAT_RX_BIP_ERR_5_OFFSET 0x2e8
#define XCMAC_STAT_RX_BIP_ERR_6_OFFSET 0x2f0
#define XCMAC_STAT_RX_BIP_ERR_7_OFFSET 0x2f8
#define XCMAC_STAT_RX_BIP_ERR_8_OFFSET 0x300
#define XCMAC_STAT_RX_BIP_ERR_9_OFFSET 0x308
#define XCMAC_STAT_RX_BIP_ERR_10_OFFSET 0x310
#define XCMAC_STAT_RX_BIP_ERR_11_OFFSET 0x318
#define XCMAC_STAT_RX_BIP_ERR_12_OFFSET 0x320
#define XCMAC_STAT_RX_BIP_ERR_13_OFFSET 0x328
#define XCMAC_STAT_RX_BIP_ERR_14_OFFSET 0x330
#define XCMAC_STAT_RX_BIP_ERR_15_OFFSET 0x338
#define XCMAC_STAT_RX_BIP_ERR_16_OFFSET 0x340
#define XCMAC_STAT_RX_BIP_ERR_17_OFFSET 0x348
#define XCMAC_STAT_RX_BIP_ERR_18_OFFSET 0x350
#define XCMAC_STAT_RX_BIP_ERR_19_OFFSET 0x358

/* Framing error counts regs */
#define XCMAC_STAT_RX_FRAMING_ERR_0_OFFSET 0x360
#define XCMAC_STAT_RX_FRAMING_ERR_1_OFFSET 0x368
#define XCMAC_STAT_RX_FRAMING_ERR_2_OFFSET 0x370
#define XCMAC_STAT_RX_FRAMING_ERR_3_OFFSET 0x378
#define XCMAC_STAT_RX_FRAMING_ERR_4_OFFSET 0x380
#define XCMAC_STAT_RX_FRAMING_ERR_5_OFFSET 0x388
#define XCMAC_STAT_RX_FRAMING_ERR_6_OFFSET 0x390
#define XCMAC_STAT_RX_FRAMING_ERR_7_OFFSET 0x398
#define XCMAC_STAT_RX_FRAMING_ERR_8_OFFSET 0x3a0
#define XCMAC_STAT_RX_FRAMING_ERR_9_OFFSET 0x3a8
#define XCMAC_STAT_RX_FRAMING_ERR_10_OFFSET 0x3b0
#define XCMAC_STAT_RX_FRAMING_ERR_11_OFFSET 0x3b8
#define XCMAC_STAT_RX_FRAMING_ERR_12_OFFSET 0x3c0
#define XCMAC_STAT_RX_FRAMING_ERR_13_OFFSET 0x3c8
#define XCMAC_STAT_RX_FRAMING_ERR_14_OFFSET 0x3d0
#define XCMAC_STAT_RX_FRAMING_ERR_15_OFFSET 0x3d8
#define XCMAC_STAT_RX_FRAMING_ERR_16_OFFSET 0x3e0
#define XCMAC_STAT_RX_FRAMING_ERR_17_OFFSET 0x3e8
#define XCMAC_STAT_RX_FRAMING_ERR_18_OFFSET 0x3f0
#define XCMAC_STAT_RX_FRAMING_ERR_19_OFFSET 0x3f8
#define XCMAC_STAT_RX_BAD_CODE_OFFSET 0x418
#define XCMAC_STAT_TX_FRAME_ERROR_OFFSET 0x458

/* Tx Histogram regs */

#define XCMAC_STAT_TX_TOTAL_PACKETS_OFFSET 0x500
#define XCMAC_STAT_TX_TOTAL_GOOD_PACKETS_OFFSET 0x508
#define XCMAC_STAT_TX_TOTAL_BYTES_OFFSET 0x510
#define XCMAC_STAT_TX_TOTAL_GOOD_BYTES_OFFSET 0x518
#define XCMAC_STAT_TX_PACKET_64_BYTES_OFFSET 0x520
#define XCMAC_STAT_TX_PACKET_65_127_BYTES_OFFSET 0x528
#define XCMAC_STAT_TX_PACKET_128_255_BYTES_OFFSET 0x530
#define XCMAC_STAT_TX_PACKET_256_511_BYTES_OFFSET 0x538
#define XCMAC_STAT_TX_PACKET_512_1023_BYTES_OFFSET 0x540
#define XCMAC_STAT_TX_PACKET_1024_1518_BYTES_OFFSET 0x548
#define XCMAC_STAT_TX_PACKET_1519_1522_BYTES_OFFSET 0x550
#define XCMAC_STAT_TX_PACKET_1523_1548_BYTES_OFFSET 0x558
#define XCMAC_STAT_TX_PACKET_1549_2047_BYTES_OFFSET 0x560
#define XCMAC_STAT_TX_PACKET_2048_4095_BYTES_OFFSET 0x568
#define XCMAC_STAT_TX_PACKET_4096_8191_BYTES_OFFSET 0x570
#define XCMAC_STAT_TX_PACKET_8192_9215_BYTES_OFFSET 0x578
#define XCMAC_STAT_TX_PACKET_LARGE_OFFSET 0x580
#define XCMAC_STAT_TX_PACKET_SMALL_OFFSET 0x588
/* Reserved 0x0590 to 0x05B0  */

#define XCMAC_STAT_TX_BAD_FCS_OFFSET 0x5b8
/*
 * Reserved 0x05C0
 * Reserved 0x05C8
 */

#define XCMAC_STAT_TX_UNICAST_OFFSET 0x5d0
#define XCMAC_STAT_TX_MULTICAST_OFFSET 0x5d8
#define XCMAC_STAT_TX_BROADCAST_OFFSET 0x5e0
#define XCMAC_STAT_TX_VLAN_OFFSET 0x5e8
#define XCMAC_STAT_TX_PAUSE_OFFSET 0x5f0
#define XCMAC_STAT_TX_USER_PAUSE_OFFSET 0x5f8
/* Reserved 0x0600  */

/* Rx Histogram regs */
#define XCMAC_STAT_RX_TOTAL_PACKETS_OFFSET 0x608
#define XCMAC_STAT_RX_TOTAL_GOOD_PACKETS_OFFSET 0x610
#define XCMAC_STAT_RX_TOTAL_BYTES_OFFSET 0x618
#define XCMAC_STAT_RX_TOTAL_GOOD_BYTES_OFFSET 0x620
#define XCMAC_STAT_RX_PACKET_64_BYTES_OFFSET 0x628
#define XCMAC_STAT_RX_PACKET_65_127_BYTES_OFFSET 0x630
#define XCMAC_STAT_RX_PACKET_128_255_BYTES_OFFSET 0x638
#define XCMAC_STAT_RX_PACKET_256_511_BYTES_OFFSET 0x640
#define XCMAC_STAT_RX_PACKET_512_1023_BYTES_OFFSET 0x648
#define XCMAC_STAT_RX_PACKET_1024_1518_BYTES_OFFSET 0x650
#define XCMAC_STAT_RX_PACKET_1519_1522_BYTES_OFFSET 0x658
#define XCMAC_STAT_RX_PACKET_1523_1548_BYTES_OFFSET 0x660
#define XCMAC_STAT_RX_PACKET_1549_2047_BYTES_OFFSET 0x668
#define XCMAC_STAT_RX_PACKET_2048_4095_BYTES_OFFSET 0x670
#define XCMAC_STAT_RX_PACKET_4096_8191_BYTES_OFFSET 0x678
#define XCMAC_STAT_RX_PACKET_8192_9215_BYTES_OFFSET 0x680
#define XCMAC_STAT_RX_PACKET_LARGE_OFFSET 0x688
#define XCMAC_STAT_RX_PACKET_SMALL_OFFSET 0x690

#define XCMAC_STAT_RX_UNDERSIZE_OFFSET 0x698
#define XCMAC_STAT_RX_FRAGMENT_OFFSET 0x6a0
#define XCMAC_STAT_RX_OVERSIZE_OFFSET 0x6a8
#define XCMAC_STAT_RX_TOOLONG_OFFSET 0x6b0
#define XCMAC_STAT_RX_JABBER_OFFSET 0x6b8
#define XCMAC_STAT_RX_BAD_FCS_OFFSET 0x6c0
#define XCMAC_STAT_RX_PACKET_BAD_FCS_OFFSET 0x6c8
#define XCMAC_STAT_RX_STOMPED_FCS_OFFSET 0x6d0

#define XCMAC_STAT_RX_UNICAST_OFFSET 0x6d8
#define XCMAC_STAT_RX_MULTICAST_OFFSET 0x6e0
#define XCMAC_STAT_RX_BROADCAST_OFFSET 0x6e8
#define XCMAC_STAT_RX_VLAN_OFFSET 0x6f0
#define XCMAC_STAT_RX_PAUSE_OFFSET 0x6f8
#define XCMAC_STAT_RX_USER_PAUSE_OFFSET 0x700

/* Rx In Range Error  */
#define XCMAC_STAT_RX_INRANGE_ERR_OFFSET 0x708
/* Packet Truncation Indicator */
#define XCMAC_STAT_RX_TRUNCATED_OFFSET 0x710

#define XCMAC_STAT_TX_JABBER_OFFSET 0x0718
#define XCMAC_STAT_TX_OVERSIZE_OFFSET 0x0720
#define XCMAC_STAT_TX_UNDERSIZE_OFFSET 0x0728
#define XCMAC_STAT_TX_TOOLONG_OFFSET 0x0730
#define XCMAC_STAT_TX_FRAGMENT_OFFSET 0x0738
#define XCMAC_STAT_TX_PACKET_BAD_FCS_OFFSET 0x0740
#define XCMAC_STAT_TX_STOMPED_FCS_OFFSET 0x0748

#define XCMAC_STAT_TX_BAD_CODE_OFFSET 0x0750

#define XCMAC_RSFEC_CONFIG_ENABLE_OFFSET 0x107C

/* @} */

/** @name Registers Masks
 *
 * Register masks for xcmac register fields
 * @{
 */
/* All register masks */

/* GT reset masks */
#define XCMAC_GT_RESET_MASK 0x1

/* RESET_REG masks */
#define XCMAC_USR_RX_SERDES_RESET_MASK 0x3ff
#define XCMAC_RX_CORE_RESET_MASK 0x40000000
#define XCMAC_TX_CORE_RESET_MASK 0x80000000

/* CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1 masks */
#define XCMAC_CONFIG_TX_FLOW_CONTROL_REG1_MASK 0x1FF

#define XCMAC_CTL_RX_ENABLE_GCP_BIT 10
#define XCMAC_CTL_RX_ENABLE_PCP_BIT 11
#define XCMAC_CTL_RX_ENABLE_GPP_BIT 12
#define XCMAC_CTL_RX_ENABLE_PPP_BIT 13

#define XCMAC_CTL_RX_ENABLE_GCP_BIT_MASK 0x400
#define XCMAC_CTL_RX_ENABLE_PCP_BIT_MASK 0x800
#define XCMAC_CTL_RX_ENABLE_GPP_BIT_MASK 0x1000
#define XCMAC_CTL_RX_ENABLE_PPP_BIT_MASK 0x2000

/* CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2 masks */
#define XCMAC_CTL_RX_CHECK_MCAST_GCP_BIT 0
#define XCMAC_CTL_RX_CHECK_UCAST_GCP_BIT 1
#define XCMAC_CTL_RX_CHECK_SA_GCP_BIT 2
#define XCMAC_CTL_RX_CHECK_ETYPE_GCP_BIT 3
#define XCMAC_CTL_RX_CHECK_OPCODE_GCP_BIT 4

#define XCMAC_CTL_RX_CHECK_MCAST_PCP_BIT 5
#define XCMAC_CTL_RX_CHECK_UCAST_PCP_BIT 6
#define XCMAC_CTL_RX_CHECK_SA_PCP_BIT 7
#define XCMAC_CTL_RX_CHECK_ETYPE_PCP_BIT 8
#define XCMAC_CTL_RX_CHECK_OPCODE_PCP_BIT 9

#define XCMAC_CTL_RX_CHECK_MCAST_GPP_BIT 10
#define XCMAC_CTL_RX_CHECK_UCAST_GPP_BIT 11
#define XCMAC_CTL_RX_CHECK_SA_GPP_BIT 12
#define XCMAC_CTL_RX_CHECK_ETYPE_GPP_BIT 13
#define XCMAC_CTL_RX_CHECK_OPCODE_GPP_BIT 14

#define XCMAC_CTL_RX_CHECK_OPCODE_PPP_BIT 15
#define XCMAC_CTL_RX_CHECK_MCAST_PPP_BIT 16
#define XCMAC_CTL_RX_CHECK_UCAST_PPP_BIT 17
#define XCMAC_CTL_RX_CHECK_SA_PPP_BIT 18
#define XCMAC_CTL_RX_CHECK_ETYPE_PPP_BIT 19

#define XCMAC_CTL_RX_CHECK_MCAST_GCP_BIT_MASK 0x1
#define XCMAC_CTL_RX_CHECK_UCAST_GCP_BIT_MASK 0x2
#define XCMAC_CTL_RX_CHECK_SA_GCP_BIT_MASK 0x4
#define XCMAC_CTL_RX_CHECK_ETYPE_GCP_BIT_MASK 0x8
#define XCMAC_CTL_RX_CHECK_OPCODE_GCP_BIT_MASK 0x10

#define XCMAC_CTL_RX_CHECK_MCAST_PCP_BIT_MASK 0x20
#define XCMAC_CTL_RX_CHECK_UCAST_PCP_BIT_MASK 0x40
#define XCMAC_CTL_RX_CHECK_SA_PCP_BIT_MASK 0x80
#define XCMAC_CTL_RX_CHECK_ETYPE_PCP_BIT_MASK 0x100
#define XCMAC_CTL_RX_CHECK_OPCODE_PCP_BIT_MASK 0x200

#define XCMAC_CTL_RX_CHECK_MCAST_GPP_BIT_MASK 0x400
#define XCMAC_CTL_RX_CHECK_UCAST_GPP_BIT_MASK 0x800
#define XCMAC_CTL_RX_CHECK_SA_GPP_BIT_MASK 0x1000
#define XCMAC_CTL_RX_CHECK_ETYPE_GPP_BIT_MASK 0x2000
#define XCMAC_CTL_RX_CHECK_OPCODE_GPP_BIT_MASK 0x4000

#define XCMAC_CTL_RX_CHECK_OPCODE_PPP_BIT_MASK 0x8000
#define XCMAC_CTL_RX_CHECK_MCAST_PPP_BIT_MASK 0x10000
#define XCMAC_CTL_RX_CHECK_UCAST_PPP_BIT_MASK 0x20000
#define XCMAC_CTL_RX_CHECK_SA_PPP_BIT_MASK 0x40000
#define XCMAC_CTL_RX_CHECK_ETYPE_PPP_BIT_MASK 0x80000

#define XCMAC_CAUI_MODE_MASK 0x1

#define XCMAC_CORE_MODE_MASK 0x3

/* CONFIGURATION_TX_REG1 masks */
#define XCMAC_CTL_TX_ENABLE_MASK 0x1
#define XCMAC_CTL_TX_ENABLE_EN_BIT 0
#define XCMAC_TX_TEST_PATTERN_EN_BIT 16
#define XCMAC_TX_TEST_PATTERN_EN_BIT_MASK 0x10000

#define XCMAC_CTL_TX_SEND_RFI_EN_BIT 4
#define XCMAC_CTL_TX_SEND_RFI_EN_BIT_MASK 0x10
#define XCMAC_CTL_TX_SEND_IDLE_EN_BIT 5
#define XCMAC_CTL_TX_SEND_IDLE_EN_BIT_MASK 0x20

#define XCMAC_TICK_REGISTER_EN_MASK 0x1

/* Rx flow control masks */
#define XCMAC_CTL_RX_PAUSE_ENABLE_MASK 0x1FF
#define XCMAC_CTL_RX_PAUSE_ACK_ENABLE_MASK 0xFF8000
#define XCMAC_CTL_RX_PAUSE_ACK_ENABLE_BIT 15

/* CONFIGURATION_RX_REG1 masks and shifts */
#define XCMAC_CTL_RX_ENABLE_MASK 0x1
#define XCMAC_CTL_RX_ENABLE_EN_BIT 0
#define XCMAC_CTL_RX_FORCE_RESYNC_EN_BIT 7
#define XCMAC_CTL_RX_FORCE_RESYNC_EN_BIT_MASK 0x80
#define XCMAC_RX_TEST_PATTERN_EN_BIT 8
#define XCMAC_RX_TEST_PATTERN_EN_BIT_MASK 0x100

#define XCMAC_STAT_RX_BLOCK_LOCK_MASK 0xfffff
#define XCMAC_STAT_RX_SYNCED_MASK 0xfffff
#define XCMAC_STAT_RX_SYNCED_ERR_MASK 0xfffff
#define XCMAC_STAT_RX_MF_ERR_MASK 0xfffff
#define XCMAC_STAT_RX_MF_LEN_ERR_MASK 0xfffff
#define XCMAC_STAT_RX_MF_REPEAT_ERR_MASK 0xfffff

/* STAT_RX_STATUS_OFFSET masks and shifts */

#define XCMAC_STAT_RX_MASK 0x1
#define XCMAC_STAT_RX_ALIGNED_MASK 0x2
#define XCMAC_STAT_RX_MISALIGNED_MASK 0x4
#define XCMAC_STAT_RX_ALIGNED_ERR_MASK 0x8
#define XCMAC_STAT_RX_HI_BER_MASK 0x10
#define XCMAC_STAT_RX_REMOTE_FAULT_MASK 0x20
#define XCMAC_STAT_RX_LOCAL_FAULT_MASK 0x40
#define XCMAC_STAT_RX_INTERNAL_LOCAL_FAULT_MASK 0x80
#define XCMAC_STAT_RX_RECEIVED_LOCAL_FAULT_MASK 0x100
#define XCMAC_STAT_RX_TEST_PATTERN_MISMATCH_MASK 0xE00
#define XCMAC_STAT_RX_BAD_PREAMBLE_MASK 0x1000
#define XCMAC_STAT_RX_BAD_SFD_MASK 0x2000
#define XCMAC_STAT_RX_GOT_SIGNAL_OS_MASK 0x4000

#define XCMAC_STAT_RX_STATUS_BIT 0
#define XCMAC_STAT_RX_ALIGNED_BIT 1
#define XCMAC_STAT_RX_MISALIGNED_BIT 2
#define XCMAC_STAT_RX_ALIGNED_ERR_BIT 3
#define XCMAC_STAT_RX_HI_BER_BIT 4
#define XCMAC_STAT_RX_REMOTE_FAULT_BIT 5
#define XCMAC_STAT_RX_LOCAL_FAULT_BIT 6
#define XCMAC_STAT_RX_INTERNAL_LOCAL_FAULT_BIT 7
#define XCMAC_STAT_RX_RECEIVED_LOCAL_FAULT_BIT 8
#define XCMAC_STAT_RX_TEST_PATTERN_MISMATCH_BIT 9
#define XCMAC_STAT_RX_BAD_PREAMBLE_BIT 12
#define XCMAC_STAT_RX_BAD_SFD_BIT 13
#define XCMAC_STAT_RX_GOT_SIGNAL_OS_BIT 14

/* STAT_TX_STATUS_REG masks and shifts */
#define XCMAC_STAT_TX_LOCAL_FAULT_MASK 0x1
#define XCMAC_STAT_TX_LOCAL_FAULT_BIT 0

/* STAT_STATUS_REG1 masks and shifts */
#define XCMAC_STAT_TX_PTP_FIFO_R_ERR_MASK 0x10
#define XCMAC_STAT_TX_PTP_FIFO_R_ERR_BIT 4
#define XCMAC_STAT_TX_PTP_FIFO_W_ERR_MASK 0x20
#define XCMAC_STAT_TX_PTP_FIFO_W_ERR_BIT 5

/* STAT_RX_LANE_DEMUXED masks and shifts */
#define STAT_RX_VL_DEMUXED_MASK 0xfffff

/* STAT_RX_PCS_LANE_NUM_REG */
#define XCMAC_STAT_RX_VL_NUM_0_MASK 0x3FFFFFFF
#define XCMAC_STAT_RX_VL_NUM_6_MASK 0x3FFFFFFF
#define XCMAC_STAT_RX_VL_NUM_12_MASK 0x3FFFFFFF
#define XCMAC_STAT_RX_VL_NUM_18_MASK 0x1FF
#define XCMAC_STAT_RX_VL_NUM_MASK 0x1F

/* CONFIGURATION_TX_BIP_OVERRIDE masks */
#define XCMAC_CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_MASK 0xFF
#define XCMAC_CTL_TX_LANE0_VLM_BIP7_OVERRIDE_BIT 8
#define XCMAC_CTL_TX_LANE0_VLM_BIP7_OVERRIDE_BIT_MASK 0x100
/* STAT_RX_BIP_OVERRIDE masks */
#define STAT_RX_BIP_OVERRIDE_BIP7_MASK 0xFF
#define STAT_RX_BIP_OVERRIDE_VALID_MASK 0x100
#define STAT_RX_BIP_OVERRIDE_VALID_BIT 8

/* STAT_TX_OTN_STATUS_OFFSET masks */
#define STAT_TX_OTN_STATUS_TX_REMOTE_FAULT_BIT 0x0001
#define STAT_TX_OTN_STATUS_TX_INTERNAL_LOCAL_FAULT_MASK 0x0002
#define STAT_TX_OTN_STATUS_TX_INTERNAL_LOCAL_FAULT_BIT 1
#define STAT_TX_OTN_STATUS_TX_RECEIVED_LOCAL_FAULT_MASK 0X0004
#define STAT_TX_OTN_STATUS_TX_RECEIVED_LOCAL_FAULT_BIT 2
#define STAT_TX_OTN_STATUS_TX_TEST_PATTERN_MISMATCH_MASK 0X0038
#define STAT_TX_OTN_STATUS_TX_TEST_PATTERN_MISMATCH_BIT 3
#define STAT_TX_OTN_STATUS_TX_BAD_PREAMBLE_MASK 0X0040
#define STAT_TX_OTN_STATUS_TX_BAD_PREAMBLE_BIT 6
#define STAT_TX_OTN_STATUS_TX_BAD_SFD_MASK 0X0080
#define STAT_TX_OTN_STATUS_TX_BAD_SFD_BIT 7
#define STAT_TX_OTN_STATUS_TX_GOT_SIGNAL_OS_MASK 0X0100
#define STAT_TX_OTN_STATUS_TX_GOT_SIGNAL_OS_BIT 8

/* CONFIGURATION_TX_OTN_PKT_LEN_REG masks */
#define XCMAC_CONFIG_TX_OTN_MIN_PKT_LEN_MASK 0xFF
#define XCMAC_CONFIG_TX_OTN_MAX_PKT_LEN_MASK 0x7FFF00
#define XCMAC_CONFIG_TX_OTN_MAX_PKT_LEN_BIT 8

/* CONFIGURATION_TX_OTN_CTL_REG masks */
#define XCMAC_CONFIG_TX_OTN_CTL_CHECK_SFD_MASK 0x1
#define XCMAC_CONFIG_TX_OTN_CTL_CHECK_SFD_BIT 0
#define XCMAC_CONFIG_TX_OTN_CTL_CHECK_PREAMBLE_MASK 0x2
#define XCMAC_CONFIG_TX_OTN_CTL_CHECK_PREAMBLE_BIT 1
#define XCMAC_CONFIG_TX_OTN_CTL_IGNORE_FCS_MASK 0x4
#define XCMAC_CONFIG_TX_OTN_CTL_IGNORE_FCS_BIT 2

/* GT_LOOPBACK_REG masks */
#define XCMAC_GT_LOOPBACK_CTL_BIT 1

#define STAT_RX_VL_NUMBER_0_BIT 0
#define STAT_RX_VL_NUMBER_1_BIT 5
#define STAT_RX_VL_NUMBER_2_BIT 10
#define STAT_RX_VL_NUMBER_3_BIT 15
#define STAT_RX_VL_NUMBER_4_BIT 20
#define STAT_RX_VL_NUMBER_5_BIT 25

#define XCMAC_STAT_RX_VL_NUMBER_6_BIT 0
#define XCMAC_STAT_RX_VL_NUMBER_7_BIT 5
#define XCMAC_STAT_RX_VL_NUMBER_8_BIT 10
#define XCMAC_STAT_RX_VL_NUMBER_9_BIT 15
#define XCMAC_STAT_RX_VL_NUMBER_10_BIT 20
#define XCMAC_STAT_RX_VL_NUMBER_11_BIT 25

#define XCMAC_STAT_RX_VL_NUMBER_12 0
#define XCMAC_STAT_RX_VL_NUMBER_13 5
#define XCMAC_STAT_RX_VL_NUMBER_14 10
#define XCMAC_STAT_RX_VL_NUMBER_15 15
#define XCMAC_STAT_RX_VL_NUMBER_16 20
#define XCMAC_STAT_RX_VL_NUMBER_17 25
#define XCMAC_STAT_RX_VL_NUMBER_18 0
#define XCMAC_STAT_RX_VL_NUMBER_19 5

/* Auto Negotiation and Link Training */
#define XCMAC_STAT_AN_FEC_ENABLE_BIT_MASK 0x1
#define XCMAC_STAT_AN_RS_FEC_ENABLE_BIT_MASK 0x2
#define XCMAC_STAT_AN_AUTONEG_COMPLETE_BIT_MASK 0x4
#define XCMAC_STAT_AN_PARALLEL_DETECTION_FAULT_BIT_MASK 0x8
#define XCMAC_STAT_AN_TX_PAUSE_ENABLE_BIT_MASK 0x10
#define XCMAC_STAT_AN_RX_PAUSE_ENABLE_BIT_MASK 0x20
#define XCMAC_STAT_AN_LP_ABILITY_VALID_BIT_MASK 0x40
#define XCMAC_STAT_AN_LP_AUTONEG_ABLE_BIT_MASK 0x80
#define XCMAC_STAT_AN_LP_PAUSE_BIT_MASK 0x100
#define XCMAC_STAT_AN_LP_ASM_DIR_BIT_MASK 0x200
#define XCMAC_STAT_AN_LP_RF_BIT_MASK 0x400
#define XCMAC_STAT_AN_LP_FEC_10G_ABILITY_BIT_MASK 0x800
#define XCMAC_STAT_AN_LP_FEC_10G_REQUEST_BIT_MASK 0x1000
#define XCMAC_STAT_AN_LP_EXTENDED_ABILITY_VALID_BIT_MASK 0x2000
#define XCMAC_STAT_AN_LP_ABILITY_EXTENDED_FEC_BIT_MASK 0x3c000
#define XCMAC_STAT_AN_LP_FEC_25G_RS_ABILITY_BIT_MASK 0x40000
#define XCMAC_STAT_AN_LP_FEC_25G_BASER_REQUEST_BIT_MASK 0x80000

#define XCMAC_STAT_AN_FEC_ENABLE_BIT 0
#define XCMAC_STAT_AN_RS_FEC_ENABLE_BIT 1
#define XCMAC_STAT_AN_AUTONEG_COMPLETE_BIT 2
#define XCMAC_STAT_AN_PARALLEL_DETECTION_FAULT_BIT 3
#define XCMAC_STAT_AN_TX_PAUSE_ENABLE_BIT 4
#define XCMAC_STAT_AN_RX_PAUSE_ENABLE_BIT 5
#define XCMAC_STAT_AN_LP_ABILITY_VALID_BIT 6
#define XCMAC_STAT_AN_LP_AUTONEG_ABLE_BIT 7
#define XCMAC_STAT_AN_LP_PAUSE_BIT 8
#define XCMAC_STAT_AN_LP_ASM_DIR_BIT 9
#define XCMAC_STAT_AN_LP_RF_BIT 10
#define XCMAC_STAT_AN_LP_FEC_10G_ABILITY_BIT 11
#define XCMAC_STAT_AN_LP_FEC_10G_REQUEST_BIT 12
#define XCMAC_STAT_AN_LP_EXTENDED_ABILITY_VALID_BIT 13
#define XCMAC_STAT_AN_LP_ABILITY_EXTENDED_FEC_BIT 14
#define XCMAC_STAT_AN_LP_FEC_25G_RS_ABILITY_BIT 18
#define XCMAC_STAT_AN_LP_FEC_25G_BASER_REQUEST_BIT 19

#define XCMAC_STAT_AN_LP_ABILITY_1000BASE_KX_BIT_MASK 0x1
#define XCMAC_STAT_AN_LP_ABILITY_10GBASE_KX4_BIT_MASK 0x2
#define XCMAC_STAT_AN_LP_ABILITY_10GBASE_KR_BIT_MASK 0x4
#define XCMAC_STAT_AN_LP_ABILITY_40GBASE_KR4_BIT_MASK 0x8
#define XCMAC_STAT_AN_LP_ABILITY_40GBASE_CR4_BIT_MASK 0x10
#define XCMAC_STAT_AN_LP_ABILITY_100GBASE_CR10_BIT_MASK 0x20
#define XCMAC_STAT_AN_LP_ABILITY_100GBASE_KP4_BIT_MASK 0x40
#define XCMAC_STAT_AN_LP_ABILITY_100GBASE_KR4_BIT_MASK 0x80
#define XCMAC_STAT_AN_LP_ABILITY_100GBASE_CR4_BIT_MASK 0x100
#define XCMAC_STAT_AN_LP_ABILITY_25GBASE_KR_BIT_MASK 0x200
#define XCMAC_STAT_AN_LP_ABILITY_25GBASE_CR_BIT_MASK 0x400
#define XCMAC_STAT_AN_LP_ABILITY_25GBASE_KR1_BIT_MASK 0x800
#define XCMAC_STAT_AN_LP_ABILITY_25GBASE_CR1_BIT_MASK 0x1000
#define XCMAC_STAT_AN_LP_ABILITY_50GBASE_KR2_BIT_MASK 0x2000
#define XCMAC_STAT_AN_LP_ABILITY_50GBASE_CR2_BIT_MASK 0x4000

#define XCMAC_STAT_AN_LP_ABILITY_1000BASE_KX_BIT 0
#define XCMAC_STAT_AN_LP_ABILITY_10GBASE_KX4_BIT 1
#define XCMAC_STAT_AN_LP_ABILITY_10GBASE_KR_BIT 2
#define XCMAC_STAT_AN_LP_ABILITY_40GBASE_KR4_BIT 3
#define XCMAC_STAT_AN_LP_ABILITY_40GBASE_CR4_BIT 4
#define XCMAC_STAT_AN_LP_ABILITY_100GBASE_CR10_BIT 5
#define XCMAC_STAT_AN_LP_ABILITY_100GBASE_KP4_BIT 6
#define XCMAC_STAT_AN_LP_ABILITY_100GBASE_KR4_BIT 7
#define XCMAC_STAT_AN_LP_ABILITY_100GBASE_CR4_BIT 8
#define XCMAC_STAT_AN_LP_ABILITY_25GBASE_KR_BIT 9
#define XCMAC_STAT_AN_LP_ABILITY_25GBASE_CR_BIT 10
#define XCMAC_STAT_AN_LP_ABILITY_25GBASE_KR1_BIT 11
#define XCMAC_STAT_AN_LP_ABILITY_25GBASE_CR1_BIT 12
#define XCMAC_STAT_AN_LP_ABILITY_50GBASE_KR2_BIT 13
#define XCMAC_STAT_AN_LP_ABILITY_50GBASE_CR2_BIT 14

#define XCMAC_STAT_AN_LINK_CNTL_1000BASE_KX_MASK 0x3
#define XCMAC_STAT_AN_LINK_CNTL_10GBASE_KX4_MASK 0xc
#define XCMAC_STAT_AN_LINK_CNTL_10GBASE_KR_MASK 0x30
#define XCMAC_STAT_AN_LINK_CNTL_40GBASE_KR4_MASK 0xc0
#define XCMAC_STAT_AN_LINK_CNTL_40GBASE_CR4_MASK 0x300
#define XCMAC_STAT_AN_LINK_CNTL_100GBASE_CR10_MASK 0xc00
#define XCMAC_STAT_AN_LINK_CNTL_100GBASE_KP4_MASK 0x3000
#define XCMAC_STAT_AN_LINK_CNTL_100GBASE_KR4_MASK 0xc000
#define XCMAC_STAT_AN_LINK_CNTL_100GBASE_CR4_MASK 0x30000
#define XCMAC_STAT_AN_LINK_CNTL_25GBASE_KRCR_S_MASK 0xc0000
#define XCMAC_STAT_AN_LINK_CNTL_25GBASE_KRCR_MASK 0x300000
#define XCMAC_STAT_AN_LINK_CNTL_25GBASE_KR1_MASK 0xc00000
#define XCMAC_STAT_AN_LINK_CNTL_25GBASE_CR1_MASK 0x3000000
#define XCMAC_STAT_AN_LINK_CNTL_50GBASE_KR2_MASK 0xc000000
#define XCMAC_STAT_AN_LINK_CNTL_50GBASE_CR2_MASK 0x30000000

#define XCMAC_STAT_AN_LINK_CNTL_1000BASE_KX_BIT 0
#define XCMAC_STAT_AN_LINK_CNTL_10GBASE_KX4_BIT 2
#define XCMAC_STAT_AN_LINK_CNTL_10GBASE_KR_BIT 4
#define XCMAC_STAT_AN_LINK_CNTL_40GBASE_KR4_BIT 6
#define XCMAC_STAT_AN_LINK_CNTL_40GBASE_CR4_BIT 8
#define XCMAC_STAT_AN_LINK_CNTL_100GBASE_CR10_BIT 10
#define XCMAC_STAT_AN_LINK_CNTL_100GBASE_KP4_BIT 12
#define XCMAC_STAT_AN_LINK_CNTL_100GBASE_KR4_BIT 14
#define XCMAC_STAT_AN_LINK_CNTL_100GBASE_CR4_BIT 16
#define XCMAC_STAT_AN_LINK_CNTL_25GBASE_KRCR_S_BIT 18
#define XCMAC_STAT_AN_LINK_CNTL_25GBASE_KRCR_BIT 20
#define XCMAC_STAT_AN_LINK_CNTL_25GBASE_KR1_BIT 22
#define XCMAC_STAT_AN_LINK_CNTL_25GBASE_CR1_BIT 24
#define XCMAC_STAT_AN_LINK_CNTL_50GBASE_KR2_BIT 26
#define XCMAC_STAT_AN_LINK_CNTL_50GBASE_CR2_BIT 28

#define XCMAC_STAT_LT_INITIALIZE_FROM_RX_MASK 0xF
#define XCMAC_STAT_LT_PRESET_FROM_RX_MASK 0xF0000
#define XCMAC_STAT_LT_TRAINING_MASK 0xF
#define XCMAC_STAT_LT_FRAME_LOCK_MASK 0xF0000
#define XCMAC_STAT_LT_SIGNAL_DETECT_MASK 0xF
#define XCMAC_STAT_LT_TRAINING_FAIL_MASK 0xF0000
#define XCMAC_STAT_LT_RX_SOF_BIT_MASK 0xF

#define XCMAC_STAT_LT_INITIALIZE_FROM_RX_BIT 0
#define XCMAC_STAT_LT_PRESET_FROM_RX_BIT 16
#define XCMAC_STAT_LT_TRAINING_BIT 0
#define XCMAC_STAT_LT_FRAME_LOCK_BIT 16
#define XCMAC_STAT_LT_SIGNAL_DETECT_BIT 0
#define XCMAC_STAT_LT_TRAINING_FAIL_BIT 16
#define XCMAC_STAT_LT_RX_SOF_BIT_BIT 0

#define XCMAC_CTL_AN_NONCE_SEED_BIT_MASK 0x3FC

#define XCMAC_CTL_AUTONEG_ENABLE_BIT 0
#define XCMAC_CTL_AUTONEG_BYPASS_BIT 1
#define XCMAC_CTL_AN_NONCE_SEED_BIT 2
#define XCMAC_CTL_AN_PSEUDO_SEL_BIT 10
#define XCMAC_CTL_RESTART_NEGOTIATION_BIT 11
#define XCMAC_CTL_AN_LOCAL_FAULT_BIT 12

#define XCMAC_CTL_AN_PAUSE_BIT 0
#define XCMAC_CTL_AN_ASMDIR_BIT 1
#define XCMAC_CTL_AN_CL91_FEC_REQUEST_BIT 18
#define XCMAC_CTL_AN_CL91_FEC_ABILITY_BIT 19
#define XCMAC_CTL_AN_FEC_25G_RS_REQUEST_BIT 20
#define XCMAC_CTL_AN_LOC_NP_BIT 22
#define XCMAC_CTL_AN_LP_NP_ACK_BIT 23

#define XCMAC_CTL_AN_ABILITY_1000BASE_KX_BIT 0
#define XCMAC_CTL_AN_ABILITY_10GBASE_KX4_BIT 1
#define XCMAC_CTL_AN_ABILITY_10GBASE_KR_BIT 2
#define XCMAC_CTL_AN_ABILITY_40GBASE_KR4_BIT 3
#define XCMAC_CTL_AN_ABILITY_40GBASE_CR4_BIT 4
#define XCMAC_CTL_AN_ABILITY_100GBASE_CR10_BIT 5
#define XCMAC_CTL_AN_ABILITY_100GBASE_KP4_BIT 6
#define XCMAC_CTL_AN_ABILITY_100GBASE_KR4_BIT 7
#define XCMAC_CTL_AN_ABILITY_100GBASE_CR4_BIT 8
#define XCMAC_CTL_AN_ABILITY_25GBASE_KR_BIT 9
#define XCMAC_CTL_AN_ABILITY_25GBASE_CR_BIT 10
#define XCMAC_CTL_AN_ABILITY_25GBASE_KR1_BIT 11
#define XCMAC_CTL_AN_ABILITY_25GBASE_CR1_BIT 12
#define XCMAC_CTL_AN_ABILITY_50GBASE_KR2_BIT 13
#define XCMAC_CTL_AN_ABILITY_50GBASE_CR2_BIT 14

#define XCMAC_CTL_LT_RX_TRAINED_BIT_MASK 0x7
#define XCMAC_CTL_LT_PRESET_TO_TX_BIT_MASK 0x7
#define XCMAC_CTL_LT_INITIALIZE_TO_TX_BIT_MASK 0x7
#define XCMAC_CTL_LT_PSEUDO_SEED0_BIT_MASK 0x7FF
#define XCMAC_CTL_LT_PSEUDO_SEED1_BIT_MASK 0x7FF0000
#define XCMAC_CTL_LT_PSEUDO_SEED2_BIT_MASK 0x7FF
#define XCMAC_CTL_LT_PSEUDO_SEED3_BIT_MASK 0x7FF0000

#define XCMAC_CTL_LT_TRAINING_ENABLE_BIT 0
#define XCMAC_CTL_LT_RESTART_TRAINING_BIT 1
#define XCMAC_CTL_LT_PSEUDO_SEED0_BIT 0
#define XCMAC_CTL_LT_PSEUDO_SEED1_BIT 16
#define XCMAC_CTL_LT_PSEUDO_SEED2_BIT 0
#define XCMAC_CTL_LT_PSEUDO_SEED3_BIT 16

#define XCMAC_STAT_LT_K_P1_FROM_RX0_BIT_MASK 0x3
#define XCMAC_STAT_LT_K0_FROM_RX0_BIT_MASK 0xc
#define XCMAC_STAT_LT_K_M1_FROM_RX0_BIT_MASK 0x30
#define XCMAC_STAT_LT_STAT_P1_FROM_RX0_BIT_MASK 0xc0
#define XCMAC_STAT_LT_STAT0_FROM_RX0_BIT_MASK 0x300
#define XCMAC_STAT_LT_STAT_M1_FROM_RX0_BIT_MASK 0xc00
#define XCMAC_STAT_LT_K_P1_TO_TX1_BIT_MASK 0x30000
#define XCMAC_STAT_LT_K0_TO_TX1_BIT_MASK 0xc0000
#define XCMAC_STAT_LT_K_M1_TO_TX1_BIT_MASK 0x300000
#define XCMAC_STAT_LT_STAT_P1_TO_TX1_BIT_MASK 0xc00000
#define XCMAC_STAT_LT_STAT0_TO_TX1_BIT_MASK 0x3000000
#define XCMAC_STAT_LT_STAT_M1_TO_TX1_BIT_MASK 0xc000000

#define XCMAC_STAT_LT_K_P1_FROM_RX0_BIT 0
#define XCMAC_STAT_LT_K0_FROM_RX0_BIT 2
#define XCMAC_STAT_LT_K_M1_FROM_RX0_BIT 4
#define XCMAC_STAT_LT_STAT_P1_FROM_RX0_BIT 6
#define XCMAC_STAT_LT_STAT0_FROM_RX0_BIT 8
#define XCMAC_STAT_LT_STAT_M1_FROM_RX0_BIT 10
#define XCMAC_STAT_LT_K_P1_TO_TX1_BIT 16
#define XCMAC_STAT_LT_K0_TO_TX1_BIT 18
#define XCMAC_STAT_LT_K_M1_TO_TX1_BIT 20
#define XCMAC_STAT_LT_STAT_P1_TO_TX1_BIT 22
#define XCMAC_STAT_LT_STAT0_TO_TX1_BIT 24
#define XCMAC_STAT_LT_STAT_M1_TO_TX1_BIT 26

#define XCMAC_STAT_LT_K_P1_TO_TX2_BIT_MASK 0x3
#define XCMAC_STAT_LT_K0_TO_TX2_BIT_MASK 0xc
#define XCMAC_STAT_LT_K_M1_TO_TX2_BIT_MASK 0x30
#define XCMAC_STAT_LT_STAT_P1_TO_TX2_BIT_MASK 0xc0
#define XCMAC_STAT_LT_STAT0_TO_TX2_BIT_MASK 0x300
#define XCMAC_STAT_LT_STAT_M1_TO_TX2_BIT_MASK 0xc00
#define XCMAC_STAT_LT_K_P1_TO_TX3_BIT_MASK 0x30000
#define XCMAC_STAT_LT_K0_TO_TX3_BIT_MASK 0xc0000
#define XCMAC_STAT_LT_K_M1_TO_TX3_BIT_MASK 0x300000
#define XCMAC_STAT_LT_STAT_P1_TO_TX3_BIT_MASK 0xc00000
#define XCMAC_STAT_LT_STAT0_TO_TX3_BIT_MASK 0x3000000
#define XCMAC_STAT_LT_STAT_M1_TO_TX3_BIT_MASK 0xc000000

#define XCMAC_STAT_LT_K_P1_TO_TX2_BIT 0
#define XCMAC_STAT_LT_K0_TO_TX2_BIT 2
#define XCMAC_STAT_LT_K_M1_TO_TX2_BIT 4
#define XCMAC_STAT_LT_STAT_P1_TO_TX2_BIT 6
#define XCMAC_STAT_LT_STAT0_TO_TX2_BIT 8
#define XCMAC_STAT_LT_STAT_M1_TO_TX2_BIT 10
#define XCMAC_STAT_LT_K_P1_TO_TX3_BIT 16
#define XCMAC_STAT_LT_K0_TO_TX3_BIT 18
#define XCMAC_STAT_LT_K_M1_TO_TX3_BIT 20
#define XCMAC_STAT_LT_STAT_P1_TO_TX3_BIT 22
#define XCMAC_STAT_LT_STAT0_TO_TX3_BIT 24
#define XCMAC_STAT_LT_STAT_M1_TO_TX3_BIT 26

/* RS_FEC Enable */
#define XCMAC_RSFEC_CONFIG_RX_ENABLE_MASK 0x1
#define XCMAC_RSFEC_CONFIG_TX_ENABLE_MASK 0x2
#define XCMAC_RSFEC_CONFIG_RX_ENABLE_BIT 0x1
#define XCMAC_RSFEC_CONFIG_TX_ENABLE_BIT 0x2

/* @} */

#endif /* end of protection macro */
